Presettable frequency divider for electronic timepiece

ABSTRACT

An electronic timepiece in which the output of a stable, highfrequency standard such as a crystal oscillator, is fed to a presettable frequency-divider to produce periodic low-frequency output pulses for actuating a time display. The frequency of the oscillator lies in a range somewhat below an assigned value producing, upon division, the desired number of output pulses for accurate timing, the resultant deficiency being made up by adding pulses to input stages of the divider sufficient to compensate therefor. In this way, one may manufacture crystals under far less restrictive tolerances than those imposed when the crystal is required to operate at the assigned frequency.

United States Patent 1191 Koehler et al.

[451 Dec. 11, 1973 PRESETTABLE FREQUENCY DIVIDER FOR 3,540,207 ll/l970 Keeler 58/23 R C RON TIMEPIECE 3,629,582 12/197] Koehler 58/23 R 3,646,751 3/1972 Purland et al.... 58/50 R [75] Inventors: a Koehler, Westwood; Jerrald 3,653,204 4/1972 Miwa 58/4 A A. Zupfer, River Vale; Jan Willem Prflk, Hackensack, of Primary Examiner-Richard B. Wilkinson [73] Assignee: Bulova Watch Company, Inc., New Assistant Jackmon York, Attorney-Michael Ebert [22] Filed: Aug. 27, 1971 [57] ABSTRACT PP 175,662 An electronic timepiece in which the output of a stable, high-frequency standard such as a crystal oscilla- 52 U.S. Cl. 58/23 R, 58/50 R, 58/855, is fed to a Presettable frequency-divider to P 328/44 duce periodic low-frequency output pulses for actuat- 51 Int C| G04 3,00 04 19/00 04 27/00 ing a time display. The frequency of the oscillator H68 [58] Field of Search 58/4 A, 23 R, 23 A, in a range Smewhatbe1ow an assigned value P ing, upon division, the desired number Of output 331/158. 328/39, 44, pulses for accurate timing, the resultant deficiency being made up by adding pulses to input stages of the [56] References Cited divider sufficient to compensate therefor. ln this way, UNITED STATES PATENTS one may manufacture crystals under far less restrictive tolerances than those imposed when the crystal is reg f et a1 25 quired to operate at the assigned frequency. ar 1 3,541,779 1l/1970 Lan ley 58/23 R X 12 Claims, 5 Drawing Figures I j Z file/Nana: 5c77cw \SflPPLEfif/YTAL v I [By/ 9 H /r/os/g (By/*1) I I 75 Jr/2 6 L [3 HD5657- /4 BP'SEf/ABE p/woaa I PAIENIEB DEC 1 1 I975 SHEETZHFZ T1 El.&.

FROM K 'M T /5 l eoseemwaw I -D Q Q Min/0e) 0 0- I CL m. CL E a a 6- 2 E l A! 'l J 27W: lo Z 6774665 Soc/m6 72 677966 Damage 'Q D Q FFI I N VENTORS PRESETTABLE FREQUENCY DIVIDER FOR ELECTRONIC TIMEPIECE BACKGROUND OF THE INVENTION This invention relates generally to electronic timepieces, and more particularly to a timing system in which low-frequency periodic pulses for actuating a time display are derived from a presettable frequencydivider coupled to a stable high-frequency source.

In order to provide an electronic timepiece of high accuracy, it is known to derive periodic pulses at a low repetition rate from a non-settable frequency-divider coupled to a high-frequency standard, the pulses serving to actuate a suitable time display. The frequency standard or time base is generally in the form of a piezoelectric crystal-controlled oscillator or any other highly stable high-frequency source. The time display is adapted to indicate time in terms of seconds, minutes and hours, and it is therefore necessary to divide'down the frequency of the time base to a low rate suitable for the associated display.

Thus in U.S. Pat. No. 3,540,209 of Zatsky et al., an electronic timepiece is disclosed wherein pulses at a rate of one per second are generated, the pulses serving to actuate a liquid-crystal display for indicating the passage of time. For this purpose, use is made of a crystalcontrolled oscillator operating at a frequency of 32,768 Hz, the output of the oscillator being applied to a chain of binary divider stages yielding an output of exactly one pulse per second.

In a similar timepiece arrangement disclosed in U.S. Pat. No. 3,540,207 to Keeler, a crystal-controlled time base operating at a frequency of 16,384 Hz is divided down by fourteen binary stages in tandem to yield one pulse per second for actuating a motor driving the gears of a conventional mechanical display having timeindicating hands. In the Langley U.S. Pat. No. 3,485,033, the frequency of a crystal-controlled oscillator is divided down to produce one pulse per minute for activating an electronic display using light-emitting diodes.

In the Schaller U.S. Pat. No. 3,282,042, the frequency of a crystal-controlled oscillator is divided down to produce a 360 Hz pulsatory output for synchronizing the operation of a tuning-fork resonator. driving thegear works of a mechanical time display.

Thus various forms of mechanical and nonmechanical time displays have heretofore been used in conjunction with a stable high-frequency time base functioning in combination with a frequency divider to reduce the frequency to a rate appropriate to the display.

The crux of the timepieces disclosed in the abovenoted patents lies in the crystal-controlled oscillator. This high-Q oscillator not only has the advantage of being inherently more stable than other species of frequency standards, but it is further characterized by an insensitivity to position error. When, therefore, the timepiece is in the form of a wrist watch, the frequency of the standard and hence the timing of the watch, is not adversely affected by changes in attitude.

A conventional crystal-controlled timepiece is a precise timekeeper only if the crystal is dimensioned to function at an assigned frequency. Thus in one of the examples previously given, one pulse per second for actuating the display, is produced by dividing down the output of a crystal oscillator operating at a frequency of exactly 32,768 Hz. Should the crystal frequency be displaced from this particular value, the timepiece will be inaccurate to an extent depending on the degree of displacement. An error of only one part in 10 thousand in the crystal frequency will give rise to a timekeeping error of about ten seconds a day or five minutes a month. This error, under modern standards of accuracy for electronic watches, is unacceptable.

Assuming that the frequency divider in the timekeeping system is an invariable element, the only means for assuring precise timekeeping is to provide a crystal operating at the assigned frequency. Though it is possible to manufacture crystals at a predetermined frequency, the processes involved are elaborate and costly. Highly trained personnel are required to carry out the techniques entailed in exactly dimensioning a crystal so that it operates at an assigned frequency.

In mass producing electronic timepieces, it is not feasible to require crystals operating precisely at an assigned frequency, for the expenses entailed in making such crystals are such as to raise production costs to a prohibitive level.

Alternatively, it is possible to incorporate the crystal in an oscillator circuit having an adjustable reactor or a group of reactors which are selectively switched into the crystal circuit in order to slightly shift the oscillator frequency so that it operates at an assigned value. Should the deviation be fairly large, it is not possible even with large reactance values, to bring the oscillator frequency to the assigned value.

Moreover when capacitors or other reactors are introduced into the crystal circuit to produce an output frequency which is displaced from the natural frequency of the crystal, the efficiency of the crystal system is impaired. Thus if the natural frequency of the crystal deviates from an ideal value more than 0.001 or 0.002 percent, it is not feasible by means of adjustable reactors, to effect the necessary correction.

SUMMARY OF THE INVENTION In view of the foregoing, it is the main object of this invention to provide an electronic timepiece making use of a presettable frequency divider in conjunction with a stable high-frequency standard to produce periodic low-frequency pulses for actuating a time display, which divider makes it possible to employ a standard whose frequency is displaced by relatively large amounts from the exact or ideal value normally required to afford precise time indications.

More specifically, it is an object of this invention to provide an arrangement of the above-described type wherein the frequency standard includes a crystal resonator whose frequency lies in a range slightly below said ideal value, whereby the crystal, since it need not meet highly restrictive tolerances, may be mass produced at reasonable cost.

Also an object of the invention is to provide a system including a presettable frequency divider operating in conjunction with a high-frequency standard whose frequency lies slightly below the ideal value at which the resultant low-frequency pulses are yielded at the desired repetition rate, which system is arranged to add pulses to the divider to an extent compensating for the deficiency of the standard.

Also an object of this invention is to provide a presettable divider of the above type which may be constructed as an integrated circuit and which may be readily adjusted to add the required number of pulses to the clock pulsessupplied by the standard.

Briefly stated, these objects are attained in a system wherein clock pulses from a high-frequency time standard whose frequency is somewhat below an ideal frequency, are applied to the main divider section of a presettable divider circuit having a predetermined number of binary divider stages, which number is such as to yield with respect to an ideal high-frequency, low frequency output pulses for activating a time display at a rate affording precise time indication.

In order to provide the proper number of output pulses despite the displacement of the standard frequency from the ideal frequency, the output pulses from the main divider section are applied to a supplemental divider section to generate a frequencyadjustment control pulse at a rate depending on the number of supplemental stages. The control pulse is applied to a preset section coupled to selected stages of the main divider section, which preset section is adjustable to introduce a correction number in the main divider section compensating for the deficiency in the standard frequency whereby the total number of pulses yielded by the main divider, within a given period, is equal to the number of pulses that would have been yielded had the standard operated at the ideal frequency.

OUTLINE OF THE DRAWING For a better understanding of the invention as well as other objects and further features thereof, reference is made to the following detailed description to be read in conjunction with the accompanying drawing, wherein:

FIG. 1 is a block diagram showing the basic sections of a presettable frequency divider circuit in accordance with the invention, the circuit operating in conjunction with a timing display system;

FIG. 2 illustrates the logic circuit of one preferred embodiment of the presettable divider;

FIG. 3 is a block diagram of a presettable divider in accordance with the invention, using electronic rather than mechanical switching means for adjusting the divider;

FIG. 4 shows the logic circuit for the presettable divider illustrated in FIG. 3, and

FIG. 5 is a block diagram of the logic circuit of another embodiment of the presettable divider.

DESCRIPTION OF THE INVENTION Referring now to FIG. 1, there is shown in block diagram the basic elements of an electronic timing system in accordance with the invention. The system includes a stable, high-frequency time source 10, preferably in the form of a crystal-controlled oscillator having an output frequency f,,. The output of oscillator is fed to a presettable divider arrangement including a main divider section 11 having n stages of binary division to produce output pulses at the desired rate for actuating a time display 12.

Display 12 may be in any available form, such as a liquid-crystal time indicator, an electro-luminescent time indicator or a mechanical time indicator. The nature of the display forms no part of the present invention except that it must be of the type which can be actuated or synchronized by timed, low-frequency pulses.

The frequency f, of oscillator 10 lies within a range slightly below that of an ideal frequency f at which, as suming a non-settable frequency divider having n stages rather than a presettable divider of the same number of stages, would yield the desired output (i.e. 1 Hz). Thus ideal frequencyf= 2".

In other words, the number of stages in main divider section 11 is such as to provide a 1 Hz signal from a 2" Hz source. If, therefore, one wishes, with a time source having a frequency f, slightly lower than frequency f, to produce output pulses which average f/n I-Iz, it is necessary to add an appropriate number of pulses to the main divider section to obtain this result.

This addition of pulses is accomplished in the presettable divider by means of a supplemental divider section 13 coupled to the output of main divider section 11. The supplemental divider section is provided with m stages to yield a frequency adjustment increment or resolution of one part in 2" The main divider section 11 cooperates with a preset section 14 coupled to the output of supplemental divider section 13, the preset section furnishing appropriate inputs to the preliminary stages (L) of the main divider. By so providing inputs to the L stages of the main divider section, one determines the upper limit to the frequency adjustment range; namely 2'" 1 parts in 2" Let us now assume that the ideal frequency f= 2 32,768 Hz. This assumption dictates 15 stages (n 15) of binary division in the main divider section to produce a 1 Hz signal for driving display 12 whose smallest time unit is one second. Let us further assume a supplemental divider section 13 having five additional stages (m 5), yielding a resolution of one part in 2 or about one part per million. This is equivalent to a frequency adjustment increment of 0.08 seconds per day.

Thus main divider section 11 in combination with supplemental divider section 13 creates a divider chain of 20 stages. If we now allow for one additional input to each of the first six stages of the presettable divider, one obtains a total frequency adjustment range of 2 1 parts in 2" or 63 parts in 2 7 or 60 parts per million. This upper limit of the frequency adjustment range is equivalent to 5.2 seconds per day.

An alternative method to setting in a number in the first L stages of the main divider section once in every 2" input pulses, is to enter an additional pulse in the first stage of'the divider up to 2' times during a complete cycle of the divider. By distributing the additional pulses evenly over the cycle, irregularity in a relatively high output frequency can be obviated.

It should be understood at this point that m can be zero, in which event the resolution is 1 Hz in 2" Hz; and also that L can be one, in which case the adjustment range is one part in 2" Moreover, should a resolution of one part in 2" be greater than is desired, then m can be made negative. Under this circumstance, no supplemental dividing stage is required at all, and a feedback output may be generated at the (nm) stage in the divider chain.

In the present arrangement, the presettable divider functions to add pulses at the input of the main divider section to make up for a deficiency in the output of the high-frequency oscillator whose frequency f, is slightly less than the ideal frequency f. The presettable divider therefore acts in an additive way to furnish the requisite number of pulses to make the output, on the average, equal to flu Hz.

Let us now consider the significant practical advantages of the present invention. The resonant frequency of a crystal depends on the dimensions of the crystal slab and the relationship between the geometry of the slab and the geometry of the crystal structure. In the standard manufacturing process, the crystal is first cut to a size approaching its assigned frequency, and then by extended lapping techniques, the crystal dimensions are slowly reduced until the frequency of the crystal reaches its assigned value. This means that great care must be exercised to prevent overshooting the assigned frequency, for once this happens, the crystal must be rejected.

But with the present invention, no high order of skill is required, for the tolerances are more liberal and the crystal is acceptable as soon as its frequency is fairly close to the ideal value f. Since the presettable divider associated with the crystal is adjustable within certain limits, it is not necessary to grind the crystal to a specific frequency value as long as the actual value is somewhat less than the ideal frequency f. This facilitates the mass production of crystals at relatively low cost.

Realizing that the binary system is capable of generating any decimal number, let us now consider as an example, an ideal frequency f equal to 10,000 Hz, a desired resolution of one part in one million and a frequency adjustment range of one part in a thousand. We shall now assume that the actual frequency f, of the time source is equal to 9998.65 Hz. It becomes necessary therefore to add 135 pulses every 100 seconds.

In other words, in a period of 100 seconds, using an ideal time base frequency f of 10,000 Hz, exactly one million pulses will be produced. But with an actual time base f of 9998.65 Hz, only 999,865 pulses will be produced in 100 seconds, resulting in a deficiency of 135 pulses which must be made up to provide accurate time indications.

In this example, our resolution requirement dictates six decimal stages, an output frequency of 1 Hz requires four decimal stages, and our adjustment range requires three inputs. The addition of 135 pulses calls for settings as follows: hundreds input, one; tens inputs, three; and ones input, five. I

After counting for one million pulses, a feedback output is generated at the end of the divider chain, the sixth decimal stage, which is fed back to the input stages to set into the first three stages the number 135. Subsequent pulses from the time source are then counted in the normal way, although the counting process has begun at 135 instead of zero.

In this fashion, for every one million pulses processed through the divide-by-n (10,000 in this case) counter, 135 will have been generated from the preset function and 999,865 pulses will have originated in the time source. These one million pulses will be seen by the time display as 100 pulses and hence l00'seconds will be displayed. It follows therefore that the 999,865 pulses generated in the 100 seconds of displayed time will be a reflection of the true count rate, 9998.65 Hz.

In the case of the alternative circuit, we would again have six decimal stages for the required resolution and four decimal stages for the output. Here too in a 100 second period, we must add 135 pulses, one every onetenth second for the first 13.5 seconds, and no pulses for the next 86.5 seconds. This is achieved by using the last three decimal stages to obtain a pulse of 13.5 seconds every seconds. This pulse is gated with the 10 Hz output to produce pulses, one every one-tenth second. These are then used to add a pulse to the first divider stage. One way this can be accomplished is by resetting the first stage to 0 when it is in the 9th state.

Referring now to FIG. 2, there is shown the logic circuit necessary to perform the preset function in the presettable divider composed of the main divider section 11, the supplemental divider section 13, and the preset section 14. Conventional symbols are used to represent flip-flop and gating functions.

The main divider section is composed of an appropriate number of binary counter stages 11,, 11 11,, 11,, to 1 1 the preliminary stages 1 l 11,, and 11 of which constitute the L stages. The supplemental or m divider section 13, which is coupled to the output of the main divider section, is shown with a first stage 13,, and a last stage 13,

The output of time source 10 is applied to the divider chain and when the m" divider section has attained full count, its last stage 13,, generates a pulse which is applied to and sets a flip-flop FFl. Flip-flop FFl is associated both with a first AND gate G and a second AND gate G one input of each gate being coupled to time source 10. The other input of gate G is connected to the Q output of flip-flop FFl while the other input of gate G is connected to the Q output thereof. When flip-flop FFl is set by a pulse from the last stage 13,, of the supplemental divider section, this setting operation disables gate G and at the same time enables gate G The output of gate G is coupled by way of three single throw-double pole switches S 8,, and S to the L stages 11 11,, and 11,, respectively, of the main divider section 11 when these switches engage their x contacts, as shown. But when switches S 8,, and S engage their y contacts, they are connected logical 0 and gate G is disconnected from the L stages.

In operation, as pointed out previously, flip-flop FFl is set by a pulse derived from the last stage 13,, in the chain, which enables Gate G The next clock pulse from time source 10 then sets the L stages (11 11,, and 11 of the main divider section to the state determined by the setting of switches 8,, 8,, and 8,.

If switch 8,, is in its x position, then the next clock pulse sets the associated binary stage 11,, to the 1 state, but if switch 8,, is on the y contact, then the clock pulse has no effect on the binary stage which remains in the 0 state. The same results are obtained with respect to switch 8,, and its associated binary stage 11,,, as well as with switch S and its associated binary stage 11,. (All L stages occupy their-0 states when the supplemental divider has reached full count to produce a pulse to set flip-flop FFl).

Associated with flip-flop FFl is flip-flop FFZ, whose C input is coupled to time source 10 and whose D input is connected to the Q output of flip-flop FFl. Hence the same clock pulse acting to enable gate G also sets flip-flop FF2, in that its D input was placed at the 1 level by the setting of flip-flop FFl. When flip-flop FFZ sets, this generates an output at its Q output which is applied to reset R of flip-flop FFl to reset this flip-flop, thereby causing gates G and G to revert to their original states in which Gate G is enabled and gate G disabled.

The L stages of main divider section 11 are now connected as a ripple counter, which means that the counter with the next clock pulse from time source 10,

counts up or begins from the pre-set number (i.e., 135) just set in. The next clock pulse will also reset flip-flop FF2 whose D input is at level at this point. The system is now incondition to receive a pulse from the m or supplemental divider section 13 to repeat the operation.

Switches 8,, 8,, and 8,, though shown in the drawing as mechanical in nature, may in practice, be in the form of thin film connections on an integrated or printed circuit board, which connections are capable of being abraded for opening the related switch, or resoldered for closing the switch. Thus no discrete switching elements are necessary.

In the arrangement disclosed above, the divider is preset manually by a multiple choice switching technique. Once the minumum increment of frequency adjustment is chosen (i.e. 0.1 sec/day), the range of adjustment is limited by the available choice of connections. As a practical matter, these connections can be provided within the limited space existing in a wrist watch.

We shall now, in relation to FIG. 3, consider a nonmechanical system constituted by memory elements presettable by means of electronic circuits external to the watch, either at the-time of manufacture or subsequent thereto, to provide means to regulate the timing.

In FIG. 3, switches M M M M and M at the L input stages of main divider section 11 are constituted by electronic switches. Such electronic switches, which are used only to contain the switch state information, are each formed by a memory element. The physical phenomenon incorporated in the memory element need not be electronic in nature, whereas the interrogation, the reading in and reading out of the state information, must be electrical in character in order to operate the electronic divider. For example, the memory elements may be in the form of magnetic cores, magnetic bubble devices or semiconductor devices.

Operation of switches M,, to M is effected by a programmable memory element 15, consisting of an L stage binary counter with a reset input Y and signal input X. Signal pulses fed into input X are counted by the memory element, and if the number of pulses fed in is less than 2 1, this number will appear in binary form at the switching points M,, to M For example, if six pulses are fed into the counter, the output stages will appear as A 0, B l, C l, D (and following) 0. These states constitute the settings of the switches M M,,, M,, M etc. necessary for the presettable divider.

Physical size limitations are the primary determining factors for the upper limit of the frequency adjustment range in the mechanical switching version shown in FIG. 2, but such limitations are not imposed in the FIG. 3 arrangement. We can, therefore, as far as the presettable divider is a determining factor, allow an adjustment range of the order of percent or more of the input frequency itself, thereby greatly extending the allowable manufacturing tolerances with respect to the frequency of the time base.

FIG. 4 shows in greater detail one embodiment of the electronic logic circuitry necessary to perform the electronic presettable feature. The AND gates M M etc.,

replace the mechanical switches shown in FIG. 2. The outputs from these AND gates are analogous to the outputs of the mechanical switches and feed to the NOR gates connected to the C inputs of the flip-flops.

The inputs to these AND gates from the programmable memory are analogous to the positions of the mechanical switches.

That is, a logic 1 level at its input is electronically the same as if the mechanical switch were in its down" or closed position (again refer to FIG. 2), while a logic 0 at its input is the same as saying the mechanical switch is in the up or open position. The logic level at each input is controlled by the state of the corresponding flip-flop. These flip-flops are connected to gether to form a ripple counter, and additionally if this counter counts in the same manner as the n and/or m divider, then this counter need only to receive the number of pulses equal to the preset number required. In the example previously given, the preset number is 135. Therefore, if pulses are fed into the counter after it has been reset to zero, then these flip-flop stages will be in the proper state so that 135 will be set into the n divider when the system requires it.

The programmable memory is programmed by connecting the X and Y inputs to an external circuit. This circuit first applies a pulse to the Y input thereby resetting all stages to zero. Next the circuit applies a number of pulses to the X input numerically equal to the preset number. The memory now retains this number until it is changed again by the external circuit.

Referring now to FIG. 5, there is shown still another embodiment of a logic circuit for a presettable divider in which the output stage of the supplemental or m divider section is applied to a third flip-flop FF3. When the m divider has reached its full count, the pulse yielded thereby will trip FF3 and start an 0" state pulse on the reset R line of flip-flop FF3 for a duration determined by the states of the input lines associated with the L stages of the divider chain. These lines are connected to an 0 or a l depending on the desired frequency adjustment.

When this pulse ends, the Q output of flip-flop FF 3 returns to the 1 state. This output gated with the Q output of the m n L" stage of the divider produces a series of pulses at the input of flip-flop FF2, the number of which is equal to the complement of the binary number on the L input lines. One of these pulses will remove the 1 state from the reset line of FF].

When the first divider stage next. reaches the I state, it will trip flip-flop FF] which resets the first divider stage to the 0 state, thereby adding one pulse. When the input of the divider changes to a 0 state, flip-flop FF2 is reset, thereby removing the 1 state from the reset line of the first divider stage and allowing the next input pulse to trip it. The system is now in readiness for the next pulse to flip-flop FF2.

While there have been shown and described preferred embodiments of a presettable frequency divider for electronic timepieces in accordance with the invention, it will be appreciated that many changes and modifications may be made therein without, however, departing from the essential spirit of the invention. For example, in lieu of a crystalled-controlled oscillator as a high-frequency standard, one may use a radioactive timekeeping standard of the type disclosed in US. Pat. No. 3,629,582.

In these patent applications, use is made of a radioactive source having a prolonged half-life, alpha particulate emanations from the source being converted into electrical pulses which are then scaled down to produce low-frequency control pulses at a constant rate.

By the use of a presettable frequency divider in accordance with the present invention, one may obtain control pulses at a desired rate.

We claim:

1. A timing system for producing low-frequency control pulses to actuate a time display as well as other pulse-actuatable devices requiring accurately-timed control pulses, said system comprising:

A. a high-frequency standard whose operating frequency is somewhat below an ideal frequency,

B. a main frequency divider coupled to the standard and having a series of binary stages in tandem relation to divide the operating frequency of the standard by an integer 2", where n is equal to the number of stages, to produce said low-frequency control pulses which within a given time period, have a deficient count which is less than the count derivable from said ideal frequency, and

C. means to add pulses to said main divider to cause the number of control pulses yielded within said period to equal that obtainable from an ideal frequency, said means including a multi-stage supplemental divider coupled to the output of said main divider to generate supplemental pulses at a rate depending on the number of stages in said supplemental divider and means to apply said supplemental pulses to a preset section coupled to selected stages of the main divider, said preset section being adjustable to introduce a correction number in said main divider compensating for the deficiency in the count.

2. A system as set forth in claim 1, wherein said standard is a crystal-controlled oscillator.

3. A system as set forth in claim 1, wherein said standard is a radioactive time base.

4. A system as set forth in claim 1, wherein the ideal frequency is 32,768 Hz, and n is to yield output pulses at one per second.

5. A system as set forth in claim 1, wherein said preset section adjustment means includes switches for connecting said preset section to selected stages of said main divider.

6. A system as set forth in claim 5, wherein said switches are formed by connections, each of which may be closed or interrupted to make or break a connection to the associated stage.

7. A system as set forth in claim 5, wherein said switches are constituted by memory elements presettable by means of electronic circuits external to the timing system.

8. An electronic timepiece comprising:

A. a time display actuatable by low-frequency timing pulses having a predetermined count within a given time period to provide accurate indications of time,

B. a stable frequency standard whose operating frequency is somewhat below a predetermined binary value, and

C. a presettable divider coupled to said standard to derive therefrom said timing pulses for driving said time display, said divider including a main frequency divider section coupled to said standard and having a series of binary stages in tandem relation to divide the operating frequency of the standard by an integer 2", where n is equal to the number of stages, to produce low-frequency output pulses whose count falls below said predetermined count for said timing pulses, a supplemental divider section coupled to the output of said main divider section to generate control pulses at a rate depending on the number of stages in said supplemental divider section, and means to apply said control pulses to a preset section coupled to selected stages of the main divider section, said preset section being adjustable to introduce a correction number in the main divider to cause the output thereof to contain precisely the said predetermined count within a given time period.

9. A timepiece as set forth in claim 8, wherein said time display is constituted by liquid crystal elements.

10. A timepiece as set forth in claim 8, wherein said time display is constituted by electroluminescent elements.

11. A timepiece as set forth in claim 8 wherein, said standard is constituted by a crystal-controlled oscillator provided with a crystal dimension to resonate at a frequency slightly less than said ideal frequency.

12. A timing system for producing low-frequency control pulses to actuate a time display as well as other pulse-actuatable devices requiring accurately-timed control pulses, said system comprising:

A. a high-frequency standard whose operating frequency is somewhat below an ideal frequency,

B. a main frequency divider coupled to the standard and having a series of binary stages in tandem relation to divide the operating frequency by an integer 2", where n" is equal tothe number of stages to produce said low-frequency control pulses which within a given period, have a deficient count that is less than the count derivable from said ideal frequency,

C. a supplemental divider coupled to the output of said main divider to generate supplemental pulses at a rate which is still lower than the rate of the control pulses, and

D. and means to enter said supplemental pulses into said main divider to cause the number of control pulses yielded within said period to equal that obtainable from an ideal frequency. 

1. A timing system for producing low-frequency control pulses to actuate a time display as well as other pulse-actuatable devices requiring accurately-timed control pulses, said system comprising: A. a high-frequency standard whose operating frequency is somewhat below an ideal frequency, B. a main frequency divider coupled to the standard and having a series of binary stages in tandem relation to divide the operating frequency of the standard by an integer 2n, where ''''n'''' is equal to the number of stages, to produce said lowfrequency control pulses which within a given time period, have a deficient count which is less than the count derivable from said ideal frequency, and C. means to add pulses to said main divider to cause the number of control pulses yielded within said period to equal that obtainable from an ideal Frequency, said means including a multi-stage supplemental divider coupled to the output of said main divider to generate supplemental pulses at a rate depending on the number of stages in said supplemental divider and means to apply said supplemental pulses to a preset section coupled to selected stages of the main divider, said preset section being adjustable to introduce a correction number in said main divider compensating for the deficiency in the count.
 2. A system as set forth in claim 1, wherein said standard is a crystal-controlled oscillator.
 3. A system as set forth in claim 1, wherein said standard is a radioactive time base.
 4. A system as set forth in claim 1, wherein the ideal frequency is 32,768 Hz, and ''''n'''' is 15 to yield output pulses at one per second.
 5. A system as set forth in claim 1, wherein said preset section adjustment means includes switches for connecting said preset section to selected stages of said main divider.
 6. A system as set forth in claim 5, wherein said switches are formed by connections, each of which may be closed or interrupted to make or break a connection to the associated stage.
 7. A system as set forth in claim 5, wherein said switches are constituted by memory elements presettable by means of electronic circuits external to the timing system.
 8. An electronic timepiece comprising: A. a time display actuatable by low-frequency timing pulses having a predetermined count within a given time period to provide accurate indications of time, B. a stable frequency standard whose operating frequency is somewhat below a predetermined binary value, and C. a presettable divider coupled to said standard to derive therefrom said timing pulses for driving said time display, said divider including a main frequency divider section coupled to said standard and having a series of binary stages in tandem relation to divide the operating frequency of the standard by an integer 2n, where ''''n'''' is equal to the number of stages, to produce low-frequency output pulses whose count falls below said predetermined count for said timing pulses, a supplemental divider section coupled to the output of said main divider section to generate control pulses at a rate depending on the number of stages in said supplemental divider section, and means to apply said control pulses to a preset section coupled to selected stages of the main divider section, said preset section being adjustable to introduce a correction number in the main divider to cause the output thereof to contain precisely the said predetermined count within a given time period.
 9. A timepiece as set forth in claim 8, wherein said time display is constituted by liquid crystal elements.
 10. A timepiece as set forth in claim 8, wherein said time display is constituted by electroluminescent elements.
 11. A timepiece as set forth in claim 8 wherein, said standard is constituted by a crystal-controlled oscillator provided with a crystal dimension to resonate at a frequency slightly less than said ideal frequency.
 12. A timing system for producing low-frequency control pulses to actuate a time display as well as other pulse-actuatable devices requiring accurately-timed control pulses, said system comprising: A. a high-frequency standard whose operating frequency is somewhat below an ideal frequency, B. a main frequency divider coupled to the standard and having a series of binary stages in tandem relation to divide the operating frequency by an integer 2n, where ''''n'''' is equal to the number of stages to produce said low-frequency control pulses which within a given period, have a deficient count that is less than the count derivable from said ideal frequency, C. a supplemental divider coupled to the output of said main divider to generate supplemental pulses at a rate which is still lower than the rate of the control pulses, and D. and means to enter said supplemental pulsEs into said main divider to cause the number of control pulses yielded within said period to equal that obtainable from an ideal frequency. 